Generating a clock with a desired frequency and a desired phase tends to be easier when the frequency range of operation is narrower. When a relatively wide frequency range of operation is desired (e.g., on the order of hundreds of MHz), it is difficult to generate a good quality clock over the entire range. FIG. 1 shows an example of a system to generate a clock having a desired phase and desired frequency over a relatively wide frequency range. In the example shown, there is a low frequency path (100) and a high frequency path (102), each of which includes a multiphase voltage-controlled oscillator (VCO) and a phase interpolator. Each multiphase VCO generates multiple signals, each at the desired frequency but with various phases. The phase interpolator takes these signals as inputs and generates a single signal with the desired frequency and desired phase. Using a low frequency path and a high frequency path as shown, the components in each path can be “tuned” or otherwise configured to operate over the particular frequency range with the desired performance characteristics or properties (e.g., with respect to ringing or lack thereof, rise/fall times, a desired load capable of being driven by a generated clock signal, etc.).
Although the example of FIG. 1 is able to generate a clock over a relatively wide frequency range of operation, it may be desirable to reduce the amount of circuitry used. For example, some systems may require multiple clocks to be generated and multiple instances of the clock generation system shown may be included in an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), system with an embedded microprocessor or other system. Reducing circuitry (e.g., in an ASIC) reduces power consumption as well as die size (and cost corresponds to die size). It would therefore be desirable if new techniques for signal generation over a wide frequency range of operation could be developed which require less circuitry.